The present invention relates to the field of semiconductor integrated circuits and, in particular, to a silicide structure capable of use in a self-aligned contact (SAC) etch.
Semiconductor integrated circuits with high device density require the patterning of closely spaced features including, for example, active areas, insulation structures, gates for field effect transistors, narrow conductors and interconnection lines, among others.
The formation of such polysilicon, metal, or insulation structures typically requires definition of the features in structures in a layer of photoresist, on a layer of polysilicon or insulator, by exposure of the photoresist with light passing through a reticle or photomask containing the desired pattern. After exposure and development of the photoresist, the underlying layer of the substrate is etched using the patterned photoresist as a template. The masking material protects designated areas of the substrate from the etch process. Subsequent processing steps are determined according to the type of device to be fabricated.
During these processing steps, problems with the misalignment of successive mask patterns relative to one another often occur. For example, deposited contacts might not line up correctly inside contact holes, source and drain regions might not line up perfectly relative to the gate region, and connections that must be physically close, but require electrical isolation from one another, might develop short circuits.
In an effort to reduce the misalignment problems of successive mask patterns, different techniques have been introduced into the IC fabrication. One of them is the salicide (self-aligned silicide) process, where a layer of polysilicon is first patterned so that a metal deposited over the wafer could then be annealed to form a metal silicide only in the area with exposed polysilicon. The salicide process relies on the fact that certain metals, such as cobalt or titanium, react under high temperatures with silicon to form conductive silicides, but do not react with silicon oxide. The unreacted metal is subsequently etched away, leaving the silicide self-aligned to the polysilicon, and automatically aligned to gate and source/drain regions. The metal in the silicide confers a lower resistance to the gate stack line, which, in turn, increases the speed of the devices.
Another technique commonly used to align a contact with an active area is the self-aligned contact (SAC) process, which involves an anisotropic etch to form a via or a contact hole that passes through the oxide layer down to the source/drain surface. The contact hole may not be perfectly aligned with the source and drain because spacers shield the vertical walls of the gate. Spacers, however, are very thin at the top of a gate and the etch-through of the top spacers during the SAC cannot be avoided. Accordingly, the polysilicon gate is typically covered with a silicon nitride or TEOS layer to form a dielectric cap material covering the gate to protect it during a SAC etch. During the formation of the contact hole in a SAC etch, a certain amount of the nitride material is removed but a sufficient amount remains so that when conductive material is deposited in the contact hole it does not short to the gate.
Until recently, logic and memory devices were packed separately, on different chips. The salicide process was used mainly for logic circuits because it made possible higher circuit performance. Similarly, the SAC process was employed primarily for memory circuits because it allowed the reduction of the cell size of the memory unit while achieving correct contact/active area alignment. As long as the logic and memory units were on separate chips, each of the two processes could be used separately without any effect on each other or implication on the overall circuit performance.
Recently, however, advanced semiconductor chips manufactured in the industry are composed of both logic and memory devices. Thus, for performance and cost reasons, current IC integration dictates the placing of logic and memory circuit on the same chip. Further, as the feature sizes continue to decrease, it may become necessary for memory chips to use low resistance gate materials, even if the memory chips are not embedded with logic devices on the same chip.
Efforts in the semiconductor industry attempting to incorporate both logic and memory applications on a single semiconductor chip have been increasing. Nevertheless, while there are many references to both the salicide and the SAC processes, only few address their actual integration.
For example, U.S. Pat. No. 5,863,820 to Huang describes a process for the integration of SAC and salicide processes on one chip, in which the polysilicon gate pedestals are formed first, those in the memory area having a silicon nitride on top. Subsequently, spacers are grown on the vertical walls of the gate pedestals and source and drain regions are formed. The gate pedestals on the memory side are then given a protective coating of oxide (RPO). This protective coating allows the salicide process to be selectively applied only to the logic side. Once the logic side is protected, a SAC process is applied to the memory side.
The methods developed by the prior art, however, do not specifically address the problems imposed by the actual simultaneous integration of the salicide and SAC processes on the same area of the chip. For example, when a SAC process is integrated with a salicide process, further adjustments and changes are required in the etch rate, selectivity, and profile control, to name just few of them. In particular, etch selectivity is a critical issue because the current salicide gate stacks are formed without a cap layer over the top of the gate. As described above, a SAC etch process is used to allow larger contacts to be patterned without shorting the contact to the gate by etching the contact selective to a cap material formed over the gate. Thus, although metal silicides confer low resistance to gate stacks, the current gate stacks cannot undergo subsequent SAC processes because the metal silicides formed by a salicide process lack a suitable cap material.
Accordingly, there is a need for an improved method by which the SAC and the salicide processes can be used together on one chip. That is, what is needed is a silicide gate structure that can be subsequently etched under a SAC method.
The present invention provides a method for forming a silicide gate stack that can subsequently undergo a SAC etch. The present method leaves a layer of cap material on top of the silicide gate, which is sufficiently thick to protect the gate during the SAC etch. The deposited cap material is suitable for subsequent SAC processes used in contact definition at sub xe2x88x920.5 micron dimensions.
Additional advantages of the present invention will be more apparent from the detailed description and accompanying drawings, which illustrate preferred embodiments of the invention.